1. Field of the Invention
The present invention relates to a lower electrode of a capacitor, and more particularly, to a method of forming a lower electrode of a capacitor in a DRAM cell in a semiconductor wafer.
2. Description of the Prior Art
In a semiconductor process, the dynamic random access memory (DRAM) is a combination of a large number of DRAM cells. A metal oxide semiconductor (MOS) in series with a capacitor constitute the DRAM cell. The design of the capacitor of the DRAM cell involves installing two conductive layers and an insulating layer on a semiconductor wafer. The two conductive layers act as the upper and lower electrodes, respectively, and the insulating layer separates the two electrodes. When a predetermined voltage is applied to the two electrodes, charges are stored in the two electrodes and a capacitance is generated. With advancement of semiconductor processing technology, the volume of the DRAM cell is smaller. Problems arise since the reduction of the DRAM cell volume causes a proportionate decrease in capacitance. Therefore, how to increase the capacitance of the capacitor in the reduced-volume DRAM cell is a very important issue.
Please refer to FIG.1 to FIG.6. FIG.1 to FIG.6 are perspective views of the method of forming a lower electrode 25 of a stack crown capacitor on a DRAM cell. As shown in FIG.1, the semiconductor wafer 10 comprises a Si substrate 12, a first dielectric layer 14 positioned on the Si substrate 12, and a polysilicon layer 18 positioned on the first dielectric layer 14 and completely filling the contact hole 16. A contact hole 16 extends down to the Si substrate.
In the formation of the lower electrode 25 of the capacitor, the second dielectric layer 22 made of silicon oxide is formed on the surface of the first polysilicon layer 18, as shown in FIG.2. Then, an isotropic dry etching process is performed to form a dielectric block containing a vertical side wall on a predetermined region above the contact hole 16, as shown in FIG.3. Next, a second polysilicon layer 24 is deposited on the surface of the second dielectric layer 22 and the first dielectric layer 18, as shown in FIG.4. Then, an etching back process is performed to remove the second polysilicon layer 24 and the first dielectric layer 18 from the first dielectric layer 14 in a vertical direction while preserving the second polysilicon layer 24 on the vertical side wall of the second dielectric layer 22, as shown in FIG.5. Lastly, a wet etching process is performed to remove the second dielectric layer 22. The first polysilicon layer 18 and the second polysilicon layer 24 remaining on the contact hole 16 are used as the lower electrode of the capacitor 25, as shown in FIG.6.
Since the surface area of the lower electrode 25 of the capacitor is larger in the current technology, the capacitance of the capacitor can be higher and the information in the DRAM cell will not be lost by the leakage current. To prevent reduction of capacitance from the reduced volume of the DRAM cell, the surface area of the lower electrode 25 can be increased. This will increase the capacitance of the capacitor.